555 timer, is a well-known and popular circuit component in electronics. It has been used in various electronics circuits and many DIY projects. It has become an integral part of electronics industry because of its vast applications. It was first introduced around 1971 by Signetics Corporation as the SE555/NE555 and was called “THE IC TIME MACHINE”. It produces highly stable time delays or oscillations. It has two modes of operation viz. one shot or monostable and free running oscillator or astable multivibrator. With monostable operation, the time delay is controlled by one external resistor and one capacitor. With astable operation, the frequency and duty cycle are accurately controlled with two external resistors and one capacitor. There are three resistors of 5KὨ connected in series inside IC 555. Therefore, it has name as IC 555.
Application 555 timer:
- DC-DC converters.
- Digital logic probes.
- Analog frequency meters and tachometers
- Temperature measurement
- FSK generator
- Schmitt trigger
- Voltage regulators.
- Waveform generators, etc.
Features and specifications of the 555 timer are:
- It is 8-pin mini DIP (Dual Inline Package) or a 14 pin DIP.
- Temperature range: -55C to 125C.
- Power supply range: +5V to +18V
- High current capability: 200mA
- Temperature stability: 0.005%/ oc
- Adjustable duty cycle.
- The max. Power dissipation per package is 600mW.
- Output is compatible with CMOS & TTL.
Pin Configuration/Function of 555 Timer:
Pin 1: Grounded terminal
It is ground pin and all the voltages are measured with respect to this terminal.
Pin 2: Trigger terminal
The triggering pulses are applied to this pin. The trigger pin is used to feed the trigger input when 555 is set up as monostable multivibrator.
Pin 3: Output terminal
At this terminal, output is available. The load can be connected to output terminal in two ways. One way is to connect between output pin and ground pin which is called as NORMALY OFF LOAD while another way is to connect between output pin and supply pin which is called as NORMALY ON LOAD.
Pin 4: Reset terminal
If we want to reset or disable IC, a negative pulse is applied to pin 4 which will reset the IC no matter what the conditions of inputs are. When it is not used for reset, it is connected to +Vcc (pin 8) to avoid any false resetting.
Pin 5: Control voltage terminal
The threshold and trigger levels are controlled by this pin. The DC voltage at this pin is 2/3 Vcc. The external AC voltage applied to this pin is used to modulate the output waveform thus change in pulse width can be achieved. When this pin is not used, it should be bypassed to ground through a 0.01μF capacitor to avoid any noise and distortion problems.
Pin 6: Threshold terminal
This is the non-inverting input terminal of upper comparator. When the voltage at this terminal exceeds 2/3 Vcc, the o/p of comparator becomes high. This will cause the o/p voltage low.
Pin 7: Discharge terminal
This pin is connected internally to the collector of transistor and most of the times a capacitor is connected between this terminal and ground. When transistor saturates, capacitor discharges through the transistor. When the transistor is cut off, the capacitor charges at the rate determined by external resistor and capacitor.
Pin 8: Power supply (+Vcc)
A DC power supply of +5V to +18V is applied to this pin with respect to ground
Block diagram of 555 Timer:
The block diagram of IC 555 is very simple which is as shown in figure-
It consists of two comparators, an R-S flip-flop, two transistors and a resistive network. Resistive network has 3 resistors of 5KὨ which acts as a voltage divider circuit which generates two reference voltages for the two comparators used in IC 555. The reference voltage for lower comparator i.e. at point A is 1/3 Vcc and that for upper one i.e. at point B is 2/3 Vcc. Upper comparator compares threshold voltage with a reference voltage of 2/3 Vcc which is present at control voltage terminal while lower comparator compares trigger voltage with a reference voltage of 1/3 Vcc.
Outputs of both comparators are applied to the S-R flip-flop. One of the two transistors is discharge transistor of which collector is connected to pin 7. This transistor saturates or cuts off according to output state of flip-flop. The saturated transistor provides discharge path through a capacitor which is connected externally. Base of another transistor is connected to reset terminal.
The internal 5kὨ resistors act as a voltage divider network which provides 2/3 Vcc at the non-inverting terminal of upper comparator while 1/3 Vcc at the inverting terminal of lower comparator.
Upper comparator has threshold i/p (pin 6) and control voltage i/p (pin 5). Many a times, the control voltage is not used, so the control voltage equals +2/3 Vcc. Output of this comparator is applied to set(S) i/p of the flip-flop. Whenever the threshold voltage exceeds the control voltage, the upper comparator’s o/p is logic 1 and it will set the SR flip-flop. The high o/p from the flip-flop is given to the base of the discharge transistor and it gets saturated. The complemented o/p from flip-flop is applied to pin 3(output). So, the o/p at pin 3 is low. These conditions will last until lower comparator triggers the flip-flop. Even if voltage at threshold i/p falls below 2/3 Vcc, the upper comparator can’t change the o/p. That is, with the upper comparator, we get only high output.
To change the o/p to low, the voltage at trigger i/p must fall below +1/3 Vcc. When this occurs, the lower comparator’s o/p becomes logic 1 and flip-flop’s o/p is zero. The low o/p from flip-flop makes the discharge transistor off and o/p at pin 3 is high. These conditions will last irrespective of voltage on the trigger i/p. With the upper comparator, we get only low output.
It is concluded that for having low o/p, the voltage on threshold must exceed the control voltage (+2/3 Vcc) while for having high o/p, the voltage on trigger must drop below +1/3 Vcc.